CAT6095
http://onsemi.com
10
Table 8. CONFIGURATION REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
HYST [1:0]
SHDN
B7
B6
B5
B4
B3
B2
B1
B0
TCRIT_LOCK
EVENT_LOCK
CLEAR
EVENT_STS
EVENT_CTRL
TCRIT_ONLY
EVENT_POL
EVENT_MODE
Bit
Description
B15:B11
Reserved for future use; can not be written; should be ignored; will typically read as 0
B10:B9 (Note 9)
00:
Disable hysteresis
01:
Set hysteresis at 1.5癈
10:
Set hysteresis at 3癈
11:
Set hysteresis at 6癈
B8 (Note 13)
0:
Thermal Sensor is enabled; temperature readings are updated at sampling rate
1:
Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
B7 (Note 12)
0:
Critical trip register can be updated
1:
Critical trip register cannot be modified; this bit can be cleared only at POR
B6 (Note 12)
0:
Alarm trip registers can be updated
1:
Alarm trip registers cannot be modified; this bit can be cleared only at POR
B5 (Note 11)
0:
Always reads as 0 (selfclearing)
1:
Writing a 1 to this position clears an event recording in interrupt mode only
B4 (Note 10)
0:
EVENT output pin is not being asserted
1:
EVENT output pin is being asserted
B3 (Note 9)
0:
EVENT output disabled; polarity dependent
: opendrain for bit B1 = 0 and grounded for B1 = 1
1:
EVENT output enabled
B2 (Note 15)
0:
event condition triggered by alarm or critical temperature limit crossing
1:
event condition triggered by critical temperature limit crossing only
B1 (Notes 9, 14)
0:
EVENT output active low
1:
EVENT output active high
B0 (Note 9)
0:
Comparator mode
1:
Interrupt mode
9. Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
10.This bit is a polarity independent
software copy of the EVENT
pin, i.e. it is under the control of B3.
11.Writing a 1 to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns
0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 12).
12.Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.
13.The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and the
temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one
of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
14.The EVENT
output is open-drain and requires an external pull-up resistor for either polarity. The natural polarity is active low , as it allows
wired-or operation on the EVENT bus.
15.Can not be set as long as lock bit B6 is set.
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